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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
D High-Performance Static CMOS Technology
- 25-ns Instruction Cycle Time (40 MHz) - 40-MIPS Performance - Low-Power 3.3-V Design Based on TMS320C2xx DSP CPU Core - Code-Compatible With 240x and F243/F241/C242 - Instruction Set Compatible With F240/C240 On-Chip Memory - Up to 8K Words x 16 Bits of Flash EEPROM (2 Sectors) - Programmable "Code-Security" Feature for the On-Chip Flash - Up to 1K Words x 16 Bits of Data/Program RAM - 544 Words of Dual-Access RAM - Up to 512 Words of Single-Access RAM Boot ROM - SCI Bootloader Event-Manager (EV) Module (EVA), Which Includes: - Two 16-Bit General-Purpose Timers - Seven 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable: - Three-Phase Inverter Control - Center- or Edge-Alignment of PWM Channels - Emergency PWM Channel Shutdown With External PDPINTA Pin - Programmable Deadband (Deadtime) Prevents Shoot-Through Faults - One Capture Unit For Time-Stamping of External Events - Input Qualifier for Select Pins - Synchronized A-to-D Conversion - Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control
D Small Foot-Print (7 mm x 7 mm) Ideally
Suited for Space-Constrained Applications
D
D Watchdog (WD) Timer Module D 10-Bit Analog-to-Digital Converter (ADC)
- 5 Multiplexed Input Channels - 500 ns Minimum Conversion Time - Selectable Twin 8-State Sequencers Triggered by Event Manager Serial Communications Interface (SCI) Phase-Locked-Loop (PLL)-Based Clock Generation Up to 13 Individually Programmable, Multiplexed General-Purpose Input / Output (GPIO) Pins User-Selectable Dual External Interrupts (XINT1 and XINT2) Power Management: - Three Power-Down Modes - Ability to Power Down Each Peripheral Independently Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1 (JTAG) Development Tools Include: - Texas Instruments (TI) ANSI C Compiler, Assembler/ Linker, and Code Composer Studio Debugger - Evaluation Modules - Scan-Based Self-Emulation (XDS510) - Broad Third-Party Digital Motor Control Support 32-Pin VF Low-Profile Quad Flatpack (LQFP) Extended Temperature Options (A and S) - A: - 40C to 85C - S: - 40C to 125C
D
D D D D D
D D
D D
D D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio and XDS510 are trademarks of Texas Instruments. IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright 2001, Texas Instruments Incorporated
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TMS320x240xA Device Summary . . . . . . . . . . . . . . . . . 3 Functional Block Diagram of the 2401A DSP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device Reset and Interrupts . . . . . . . . . . . . . . . . . . . . . 10 DSP CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TMS320LF2401A Instruction Set . . . . . . . . . . . . . . . . . 13 Functional Block Diagram of the 2401A DSP CPU . . 15 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Event Manager Module (EVA) . . . . . . . . . . . . . . . . . . . 24
Enhanced Analog-to-Digital Converter (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial Communications Interface (SCI) Module . . . . PLL-Based Clock Module . . . . . . . . . . . . . . . . . . . . . . Digital I/O and Shared Pin Functions . . . . . . . . . . . . . Watchdog (WD) Timer Module . . . . . . . . . . . . . . . . . . Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . Migrating From Other 240xA Devices to LF2401A . . . Peripheral Register Description . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 32 35 37 39 42 43 43 63 65 73
description
PRODUCT PREVIEW
The TMS320LF2401A device, a new member of the TMS320C24x generation of digital signal processor (DSP) controllers, is part of the TMS320C2000 platform of fixed-point DSPs. The LF2401A device offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing 240x and C24x DSP controller devices, the LF2401A offers increased processing performance (40 MIPS) and a higher level of peripheral integration. See the Device Summary section for device-specific features. The LF2401A device offers a peripheral suite tailored to meet the specific price/performance points required by various applications. The LF2401A also offers a cost-effective reprogrammable solution for volume production. A password-based "code security" feature on the device is useful in preventing unauthorized duplication of proprietary code stored in on-chip Flash. Note that the LF2401A contains a 256-word boot ROM to facilitate in-circuit programming. The LF2401A offers an event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Select EV pins have been provided with an "input-qualifier" circuitry, which minimizes inadvertent pin-triggering by glitches. The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and offers up to 5 channels of analog input. The autosequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead. A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. To maximize device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs). To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger supports this family. Numerous third-party developers not only offer device-level development tools, but also system-level design and development support.
TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.
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TMS320LF2401A DSP CONTROLLER
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TMS320x240xA device summary
Table 1. Device Feature Comparison Between LF2401A and Lx2402A
FEATURE C2xx DSP Core Instruction Cycle MIPS (40 MHz) Dual-Access RAM (DARAM) RAM (16 bit word) (16-bit Single-Access RAM (SARAM) LF2401A Yes 25 ns 40 MIPS 544 512 8K 4/4 -- Yes Yes -- EVA 2 7 1 Yes Yes Yes 5 500 ns -- Yes -- 13 2 Core Supply Voltage Packaging Some pins may not be applicable to LF2401A. I/O 3.3 V 3.3 V 32-pin VF LF2402A Yes 25 ns 40 MIPS 544 512 8K 4/4 -- Yes Yes -- EVA 2 8 3/2 Yes Yes Yes 8 500 ns -- Yes -- 21 3 3.3 V 3.3 V 64-pin PG LC2402A Yes 25 ns 40 MIPS 544 -- -- -- 6K Yes -- -- EVA 2 8 3/2 Yes Yes Yes 8 500 ns -- Yes -- 21 3 3.3 V 3.3 V 64-pin PG 64-pin PAG
3.3-V Flash (Program Space, 16-bit word) Flash Sectors On-chip ROM (Program Space, 16-bit word) Code Security for On-Chip Flash/ROM Boot ROM External Memory Interface Event Manager A (EVA) S S S S General-Purpose (GP) Timers Compare (CMP)/PWM Capture (CAP)/QEP Input qualifier circuitry on PDPINTx, CAPn, XINT1/2, and ADCSOC pins
Watchdog Timer 10-Bit ADC S S SPI SCI CAN Digital I/O Pins (Shared) External Interrupts Channels Conversion Time (minimum)
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
functional block diagram of the 2401A DSP controller
VDD (3.3 V) VSS RS XF XINT1 XINT2 CLKOUT C2xx DSP Core
DARAM (B0) 256 Words
XTAL1/CLKIN PLL Clock XTAL2
DARAM (B1) 256 Words 10-Bit ADC (With Twin Autosequencer)
ADC00-ADC04 VCCA VSSA ADCSOC
DARAM (B2) 32 Words
SCITXD/IOPB3 SARAM (512 Words) SCI SCIRXD/IOPB4
VCCP (5V)
PRODUCT PREVIEW
Flash (Flash: 8K Words - 4K/4K Sectors)
WD
PDPINTA/IOPA0 PWM1/IOPA1 PWM2/IOPA2 PWM3/IOPA3 PWM4/IOPA4 PWM5/IOPA5 PWM6/IOPA6 CAP1 T2PWM Event Manager A D 1 x Capture Input D 7 x Compare/PWM Output D 2 x GP Timers/PWM
Digital I/O (Shared With Other Pins)
Port A(0-7) IOPA[0:7] Port B(0-5) IOPB[0:5]
TRST TDO/IOPB2 JTAG Port TDI/OPB5 TMS/XF TCK/IOPB1
T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0. XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
32-PIN VF PACKAGE (TOP VIEW)
24 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 13 12 11 10 9
2
3
4
5
6
7
8
TBD - Pin assignments for the 32-pin VF package to be supplied later.
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
terminal functions
Terminal Functions
TERMINAL NAME RS NO. DESCRIPTION Device reset. RS causes the device to terminate execution and to set PC = 0. When RS is brought to a high level, execution begins at location zero of program memory. () Power drive protection input. When this pin is pulled low by an external event, an interrupt is generated and all PWM outputs go to high-impedance state. PDPINTA will keep PWM outputs in high-impedance state even when the DSP is not executing. The device comes up with PDPINTA activated; however, the user can disable the PDPINTA function if needed, by writing to bit 0 of the EVAIMRA register. () This pin must be held high when on-chip boot ROM is invoked. PWM1/IOPA1 PWM2/IOPA2 PWM3/IOPA3 PWM4/IOPA4 PWM5/IOPA5 PWM6/IOPA6 Compare/PWM output 1 or GPIO () Compare/PWM output 2 or GPIO () Compare/PWM output 3 or GPIO () Compare/PWM output 4 or GPIO () Compare/PWM output 5 or GPIO () Compare/PWM output 6 or GPIO () Upon reset, this pin comes up as XINT1/IOPB0 pin. To enable the XINT1 function, the appropriate bit in the XINT1CR register must be set. No special configuration sequence is needed to use this pin as a GPIO. However, a write to the PADATDIR register is necessary to configure this pin as a general-purpose output. Configuration of this pin as T2PWM is achieved by writing a one to bit 8 of the MCRA register. Note that the value of bit 8 in the MCRA register does not affect the XINT1 functionality of this pin. The XINT1 function is enabled/disabled by the value written into the XINT1CR register and is independent of the value written in bit 8 in the MCRA register. () Upon reset, this pin can be configured as any one of the following: XINT2, ADCSOC, CAP1, or IOPA7. To configure this pin for XINT2 function, the appropriate bit in the XINT2CR register must be set. To configure this pin for ADCSOC function, the appropriate bit in the ADCTRL2 register must be set. To configure this pin for CAP1 function, the appropriate bits in the CAPCONA register must be configured. To summarize, the XINT2, ADCSOC, and CAP1 functions are enabled at the respective peripheral level. No special configuration sequence is needed to use this pin as a GPIO. However, a write to the PADATDIR register is necessary to configure this pin as a general-purpose output. This pin can also function as the CPU clock output. This is achieved by writing a one to bit 7 of the MCRA register. When CLKOUT is chosen, the internal logic for the XINT2, ADCSOC, and CAP1 sees the pin as a "1". () Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog supply voltage for ADC (3.3 V). Internally connected to VREFHI Analog ground reference for ADC. Internally connected to VREFLO .
PDPINTA/IOPA0
PRODUCT PREVIEW
T2PWM/XINT1/IOPB0
XINT2/ADCSOC/CAP1/ IOPA7/CLKOUT
ADC00 ADC01 ADC02 ADC03 ADC04 VCCA VSSA
Bolding indicates function of the device pin after reset. It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. TDI is muxed with digital output, not digital I/O. LEGEND: - Internal pullup - Internal pulldown (Typical active pullup/pulldown value is 20 A.) NOTE: On the target hardware, pins 13 and 14 of the JTAG header must be pulled high.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
terminal functions (continued)
Terminal Functions (Continued)
TERMINAL NAME SCITXD/IOPB3 SCIRXD/IOPB4 TCK/IOPB1 NO. DESCRIPTION SCI asynchronous serial port transmit data or GPIO () SCI asynchronous serial port receive data or GPIO () JTAG test clock or GPIO () JTAG test data input or GPO. When TRST is low (i.e., when the JTAG connector is not connected to the DSP), the TDI/OPB5 pin acts as an output. When RS is low, the OPB5 pin is asynchronously forced into a high-impedance state and when RS subsequently rises, it will remain in high-impedance state until software configures this pin as an output. The B5DIR bit (bit 13 of the PBDATDIR register) controls the enable to this output buffer. Bit 13 of the MCRA register will have no effect on this pin. () This pin must be held low during a reset to invoke the on-chip boot ROM. TDO/IOPB2 TMS/XF JTAG scan out, test data output or GPIO () JTAG test mode select or GPO. External flag output (latched software-programmable signal). XF is a general-purpose output pin. It is set/reset by the SETC XF/CLRC XF instruction. This pin is configured as an external flag output by all device resets. () JTAG test reset. After power-up or reset, the function of the TCK, TDI, TDO, and TMS pins will depend on the state of the TRST pin. If TRST = 1 (Test or Debugging mode), the function of these pins will be JTAG function (the GPIO and SCI functions of these pins are not available). If TRST = 0 (Functional mode), these pins function as GPIO or SCI pins, as appropriate. () Crystal/Clock input to PLL Crystal output Flash programming supply voltage Core supply (3.3 V) Core supply (3.3 V) Core ground Core ground Core ground
TDI/OPB5
TRST
XTAL1/CLKIN XTAL2 VCCP VDD VDD VSS VSS VSS
Bolding indicates function of the device pin after reset. It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. TDI is muxed with digital output, not digital I/O. LEGEND: - Internal pullup - Internal pulldown (Typical active pullup/pulldown value is 20 A.) NOTE: On the target hardware, pins 13 and 14 of the JTAG header must be pulled high.
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
memory map
Hex 0000 Program FLASH SECTOR 0 (4K) Interrupt Vectors (0000-003Fh) Reserved (0040-0043h) User code begins at 0044h FLASH SECTOR 1 (4K)
7FFF 8000
81FF 8200 87FF 8800
FDFF FE00
FEFF FF00
FFFF
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000-00FF in the program space will be occupied by boot ROM. Addresses 0040h-0043h in program memory are reserved for code security passwords. When CNF = 1, addresses FE00h-FEFFh and FF00h-FFFFh are mapped to the same physical block (B0) in program-memory space. For example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h-FEFFh are referred to as reserved. When CNF = 0, addresses 0100h-01FFh and 0200h-02FFh are mapped to the same physical block (B0) in data-memory space. For example, a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h-01FFh are referred to as reserved. Addresses 0300h-03FFh and 0400h-04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h has the same effect as a write to 0300h. For simplicity, addresses 0400h-04FFh are referred to as reserved.
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EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE
Reserved SARAM (512 words) Internal (PON = 1) Reserved (PON = 0) Reserved Reserved Reserved On-Chip DARAM (B0) (CNF = 1) Reserved (CNF = 0) On-Chip Flash Memory (Sectored)
0FFF 1000 1FFF 2000
005F 0060 007F 0080 00FF 0100 01FF 0200 02FF 0300 03FF 0400 04FF 0500 07FF 0800
09FF 0A00
0FFF 1000 6FFF 7000
7FFF 8000
FFFF
Figure 1. TMS320LF2401A Memory Map
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EEE EEE EEE EEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE
Memory-Mapped Registers/Reserved Addresses On-Chip DARAM B2 Illegal Reserved On-Chip DARAM (B0) (CNF = 0) Reserved (CNF = 1) On-Chip DARAM (B1) Reserved Illegal SARAM (512 words) Internal (DON = 1) Reserved (DON = 0) Reserved Illegal Reserved Peripheral Memory-Mapped Registers (System, WD, ADC, EV, SCI, I/O) FEFF FF00 FF0E Reserved Illegal FF0F Flash Control Mode Register FF10 FFFE Reserved Reserved FFFF SARAM (See Table 1 for details.) Reserved or Illegal
Hex 0000
Data
Hex 0000
I/O
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral memory map
Reserved Interrupt-Mask Register Reserved Interrupt Flag Register Emulation Registers and Reserved Hex 0000 005F 0060 007F 0080 00FF 0100 01FF 0200 02FF 0300 03FF 0400 04FF 0500 07FF 0800 09FF 0A00 6FFF 7000 73FF 7400 743F 7440 Hex 0000 0003 0004 0005 0006 0007 005F
Memory-Mapped Registers and Reserved On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM B0 On-Chip DARAM B1 Reserved
SCI
7050-705F
Illegal
7060-708F
Digital I/O Control Registers ADC Control Registers
7090-709F 70A0-70BF
Illegal
SARAM (512 words) Illegal
Illegal
70C0-73FF
Peripheral Frame 1 (PF1) Peripheral Frame 2 (PF2)
Event Manager - EVA General-Purpose Timer Registers Compare, PWM, and Deadband Registers Capture Registers
7400-7408 7411-7419 7420-7429 742C-7431 7432-743F
Illegal
77FF 7800 FFFF
Reserved Illegal
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EEEE EEEE EEEE EEEEEEEEE EEEEEEEEE
77EF 77F0 77F3 77F4
Code Security Passwords
Interrupt Mask, Vector and Flag Registers Illegal
Illegal
"Illegal" indicates that access to these addresses causes a nonmaskable interrupt (NMI).
Reserved
"Reserved" indicates addresses that are reserved for test.
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PRODUCT PREVIEW
EEEEEEEEE EEEEEEEEE
Illegal System Configuration and Control Registers Watchdog Timer Registers Illegal
7000-700F 7010-701F 7020-702F 7030-704F
EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE
EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
device reset and interrupts
The TMS320LF2401A software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The LF2401A recognizes three types of interrupt sources.
D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them. The LF2401A devices have two sources of reset: an external reset pin and a watchdog timer time-out (reset).
D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types: - External interrupts are generated by one of three external pins corresponding to the interrupts XINT1, XINT2, and PDPINTA. These three can be masked both by dedicated enable bits and by the CPU's interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A, SCI, and ADC. They can be masked both by enable bits for each event in each peripheral and by the CPU's IMR, which can mask each maskable interrupt line at the DSP core.
-
PRODUCT PREVIEW
D Software-generated interrupts for the LF2401A devices include:
- The INTR instruction. This instruction allows initialization of any LF2401A interrupt with software. Its operand indicates the interrupt vector location to which the CPU branches. This instruction globally disables maskable interrupts (sets the INTM bit to 1). The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction globally disables maskable interrupts. LF2401A devices do not have the NMI hardware signal, only software activation is provided. The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts. An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
-
-
-
Six core interrupts (INT1-INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to the F24x devices. The PIE manages all the peripheral interrupts from the LF2401A peripherals and are grouped to share the six core level interrupts. Figure 2 shows the PIE block diagram for hardware-generated interrupts. The PIE block diagram (Figure 2) and the interrupt table (Table 2) explain the grouping and interrupt vector maps. LF2401A devices have interrupts identical to those of the F24x devices. See Table 2 for details.
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device reset and interrupts (continued)
PIE PDPINTA ADCINT RXINT TXINT XINT1 XINT2 Level 1 IRQ GEN INT1 IMR IFR
INT2 CMP1INT CMP2INT CMP3INT T1PINT T1CINT T1UFINT T1OFINT
Level 2 IRQ GEN
CPU
INT3 T2PINT T2CINT T2UFINT T2OFINT Level 3 IRQ GEN
INT4 CAP1INT Level 4 IRQ GEN
RXINT TXINT
Level 5 IRQ GEN
INT5
ADCINT XINT1 XINT2
Level 6 IRQ GEN
INT6 IACK
PIVR & Logic PIRQR# PIACK# Data Bus Addr Bus
Interrupt from external interrupt pin. The remaining interrupts are internal to the peripherals.
Figure 2. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
interrupt request structure Table 2. TMS320LF2401A Interrupt Source Priority and Vectors
CPU INTERRUPT AND VECTOR ADDRESS RSN 0000h - 0026h NMI 0024h 0.0 0.1 0.2 0.3 0.5 0.6 0.9 0.10 0.11 INT2 0004h 0.12 0.13 0.14 0.15 1.0 INT3 0006h 1.1 1.2 1.3 INT4 0008h INT5 000Ah 1.4 1.8 1.9 BIT POSITION IN PIRQRx AND PIACKRx PERIPHERAL INTERRUPT VECTOR (PIV) N/A N/A N/A 0020h 0004h 0001h 0011h 0006h 0007h 0021h 0022h 0023h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 0033h 0006h 0007h SOURCE PERIPHERAL MODULE RS pin, Watchdog CPU Nonmaskable Interrupt EVA ADC External Interrupt Logic External Interrupt Logic SCI SCI EVA EVA EVA EVA EVA EVA EVA EVA EVA EVA EVA EVA SCI SCI
INTERRUPT NAME
OVERALL PRIORITY
MASKABLE?
DESCRIPTION
Reset Reserved NMI PDPINTA ADCINT
1 2 3 4 6 7 8 10 11 14 15 16 17 18 19 20 28 29 30 31 36 43 44
N N N Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Reset from pin, watchdog timeout Emulator trap Nonmaskable interrupt, software interrupt only Power device protection interrupt pin ADC interrupt in high-priority mode External interru t pins in high interrupt ins priority SCI receiver interrupt in high-priority mode SCI transmitter interrupt in high-priority mode Compare 1 interrupt Compare 2 interrupt Compare 3 interrupt Timer 1 period interrupt Timer 1 compare interrupt Timer 1 underflow interrupt Timer 1 overflow interrupt Timer 2 period interrupt Timer 2 compare interrupt Timer 2 underflow interrupt Timer 2 overflow interrupt Capture 1 interrupt SCI receiver interrupt (low-priority mode) SCI transmitter interrupt (low-priority mode)
PRODUCT PREVIEW
XINT1 XINT2 RXINT TXINT CMP1INT CMP2INT CMP3INT T1PINT T1CINT T1UFINT T1OFINT T2PINT T2CINT T2UFINT T2OFINT CAP1INT RXINT TXINT
INT1 0002h
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A) for more information. NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
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SPRS161 - MARCH 2001
interrupt request structure (continued) Table 2. TMS320LF2401A Interrupt Source Priority and Vectors (Continued)
CPU INTERRUPT AND VECTOR ADDRESS BIT POSITION IN PIRQRx AND PIACKRx 1.12 INT6 000Ch 1.13 1.14 000Eh N/A N/A N/A 0022h N/A 0010h-0020h PERIPHERAL INTERRUPT VECTOR (PIV) 0004h 0001h 0011h N/A N/A 0000h N/A SOURCE PERIPHERAL MODULE
INTERRUPT NAME
OVERALL PRIORITY
MASKABLE?
DESCRIPTION
ADCINT XINT1 XINT2 Reserved TRAP Phantom Interrupt Vector INT8-INT16
47 48 49
Y Y Y Y N/A N/A N/A
ADC External Interrupt Logic External Interrupt Logic CPU CPU CPU CPU
ADC interrupt (low priority) External interru t pins interrupt ins (low-priority mode) Analysis interrupt TRAP instruction Phantom interrupt vector
Software interrupt vectors INT20-INT31 N/A 00028h-0603Fh N/A N/A CPU Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A) for more information. NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
DSP CPU core
The TMS320LF2401A device uses an advanced Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures -- program and data -- for full-speed execution. This multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers between program memory and data memory. This architecture permits coefficients that are stored in program memory to be read in RAM. This, coupled with a four-deep pipeline, allows the LF2401A device to execute most instructions in a single cycle. See the functional block diagram of the 2401A DSP CPU for more information.
TMS320LF2401A instruction set
The 2401A DSP implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control. For maximum throughput, the next instruction is prefetched while the current one is being executed. addressing modes The TMS320LF2401A instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and register. In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each page containing 128 words. Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (AR0- AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
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TMS320LF2401A DSP CONTROLLER
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scan-based emulation
TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardwaredevelopment support. Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx by way of the IEEE 1149.1-compatible (JTAG) interface. The LF2401A DSP does not include boundary scan. The scan chain of the device is useful for emulation function only.
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functional block diagram of the 2401A DSP CPU
Program Bus
MUX Program Bus XTAL1 CLKOUT XTAL2 Control
NPAR
XF RS
16
PC
PAR
MSTACK
MUX
Stack 8 x 16
XINT[1-2]
2
FLASH EEPROM
Program Control (PCTRL) 16
16
Data Bus 16 3 AR0(16) AR1(16) AR2(16) ARP(3) 3 ARB(3) 3 AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) 3 16 ISCALE (0-16) Multiplier PREG(32) 32 PSCALE (-6, 0, 1, 4) 32 16 MUX ARAU(16) MUX 32 TREG0(16) 9 DP(9) 16 16 9 7 LSB from IR 16 16 16 16 MUX 16
MUX 16
32 CALU(32)
16
Memory Map Register MUX IMR (16) Data/Prog DARAM B0 (256 x 16) Data DARAM B2 (32 x 16) B1 (256 x 16) MUX 16 IFR (16) GREG (16) MUX
32 32
C ACCH(16)
ACCL(16) 32
OSCALE (0-7) 16 16 16
NOTES: A. See Table 3 for symbol descriptions. B. For clarity, the data and program buses are shown as single buses although they include address and data bits. C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU instruction set information.
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Program Bus
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Data Bus
Data Bus
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
2401A legend for the internal hardware Table 3. Legend for the 2401A DSP CPU Internal Hardware
SYMBOL ACC ARAU AUX REGS NAME Accumulator Auxiliary Register Arithmetic Unit Auxiliary Registers 0-7 DESCRIPTION 32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift and rotate capabilities An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs and outputs These 16-bit registers are used as pointers to anywhere within the data space address range. They are operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used as an index value for AR updates of more than one and as a compare value to AR. Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator shifts and rotates. 32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and provides status results to PCTRL. If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM (DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2 are mapped to data memory space only, at addresses 0300-03FF and 0060-007F, respectively. Blocks 0 and 1 contain 256 words, while block 2 contains 32 words. The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. GREG specifies the size of the global data memory space. Since the global memory space is not used in the 240x devices, this register is reserved. IMR individually masks or enables the seven interrupts. The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable interrupts. A total of 32 interrupts by way of hardware and/or software are available. 16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. 16 x 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either signed or unsigned 2s-complement arithmetic multiply. MSTACK provides temporary storage for the address of the next instruction to be fetched when program address-generation logic is used to generate sequential addresses in data space. Multiplexes buses to a common input NPAR holds the program address to be driven out on the PAB in the next cycle. 16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data bus (DWEB). PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory operations scheduled for the current bus cycle. PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential data-transfer operations. PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
C
Carry
CALU
Central Arithmetic Logic Unit
PRODUCT PREVIEW
DARAM
Dual-Access RAM
DP
Data Memory Page Pointer Global Memory Allocation Register Interrupt Mask Register Interrupt Flag Register Interrupt Traps Input Data-Scaling Shifter Multiplier Micro Stack Multiplexer Next Program Address Register Output Data-Scaling Shifter Program Address Register Program Counter Program Controller
GREG
IMR IFR INT# ISCALE MPY MSTACK MUX NPAR
OSCALE
PAR PC PCTRL
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2401A legend for the internal hardware (continued) Table 3. Legend for the 2401A DSP CPU Internal Hardware (Continued)
SYMBOL PREG NAME Product Register DESCRIPTION 32-bit register holds results of 16 x 16 multiply 0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the 32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle overhead. STACK is a block of memory used for storing return addresses for subroutines and interrupt-service routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep. 16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
PSCALE
Product-Scaling Shifter
STACK TREG
Stack Temporary Register
status and control registers Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved and restored for subroutines. The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST) instruction is used to read from ST0 and ST1 -- except for the INTM bit, which is not affected by the LST instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. Figure 3 shows the organization of status registers ST0 and ST1, indicating all status bits contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 4 lists status register field definitions.
15 ST0 ARP 13 12 OV 11 OVM 10 1 9 INTM 8 DP 0
15 ST1 ARB
13
12 CNF
11 TC
10 SXM
9 C
8 1
7 1
6 1
5 1
4 XF
3 1
2 1
1 PM
0
Figure 3. Organization of Status Registers ST0 and ST1
Table 4. Status Register Field Definitions
FIELD ARB FUNCTION Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP. Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed. Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch on the status of C. C is set to 1 on a reset. On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1 instructions. RS sets the CNF to 0.
ARP
C
CNF
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TMS320LF2401A DSP CONTROLLER
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status and control registers (continued) Table 4. Status Register Field Definitions (Continued)
FIELD DP FUNCTION Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on the unmaskable RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when a maskable interrupt trap is taken. Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV. Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset this bit, respectively. LST can also be used to modify the OVM. Product shift mode. If these two bits are 00, the multiplier's 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the SPM and LST #1 instructions. PM is cleared by RS. Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter. SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction and can be loaded by the LST #1 instruction. SXM is set to 1 by reset. Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return instructions can execute based on the condition of TC. XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset by the CLRC XF instruction. XF is set to 1 by reset.
INTM
OV
OVM
PM
PRODUCT PREVIEW
SXM
TC
XF
central processing unit The TMS320LF2401A central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both the accumulator and the multiplier. This section describes the CPU components and their functions. The functional block diagram shows the components of the CPU. input scaling shifter The TMS320LF2401A provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected to the CALU. This shifter operates as part of the path of data coming from program or data space to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations. The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros; the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit (sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to the system's performance.
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multiplier The TMS320LF2401A device uses a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated with the multiplier, as follow:
D 16-bit temporary register (TREG) that holds one of the operands for the multiplier D 32-bit product register (PREG) that holds the product
Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown in Table 5. Table 5. PSCALE Product-Shift Modes
PM 00 01 10 11 SHIFT No shift Left 1 Left 4 Right 6 DESCRIPTION Product feed to CALU or data bus with no shift Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY (multiply) instruction provides the second operand (also from the data bus). A multiplication also can be performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining of the TREG load operations with CALU operations using the previous product. The pipeline operations that run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC (LTS). Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient addresses are generated by program address generation (PAGEN) logic, while the data addresses are generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values from the coefficient table sequentially and step through the data in any of the indirect addressing modes. The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample.
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Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when using the multiply-by-a-13-bit constant
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
multiplier (continued) The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The SQRA (square / add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high half, then, is loaded using the LPH instruction. central arithmetic logic unit The TMS320LF2401A central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier. The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU is always provided from the accumulator, and the other input can be provided from the product register (PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator. The TMS320LF2401A device supports floating-point operations for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized -- that is, floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of TREG. The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result in overflow.) The CALU can execute a variety of branch instructions that depend on the status of the CALU and the accumulator. These instructions can be executed conditionally based on any meaningful combination of these status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
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central arithmetic logic unit (continued) The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation. The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it. Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the carry bit. The carry bit is set to one on a hardware reset. accumulator The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 16-31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0-15). When the postscaling shifter is used on the low word, the LSBs are zero-filled. The SFL and SFR (in-place one-bit shift to the left / right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The 2401A provides a register file containing eight auxiliary registers (AR0 - AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers also can be stored in data memory or used as inputs to the CALU. The auxiliary register file (AR0 - AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either by 1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel.
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TMS320LF2401A DSP CONTROLLER
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internal memory
The TMS320LF2401A device is configured with the following memory modules:
D D D D
Dual-access random-access memory (DARAM) Single-access random-access memory (SARAM) Flash Boot ROM
dual-access RAM (DARAM) There are 544 words x 16 bits of DARAM on the 2401A device. The 2401A DARAM allows writes to and reads from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data memory) instructions allow dynamic configuration of the memory maps through software. When using on-chip RAM, the 2401A runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of the 2401A architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. single-access RAM (SARAM) There are 512 words x 16 bits of SARAM on the LF2401A. The PON and DON bits select SARAM (512 words) mapping in program space, data space, or both. See Table 15 for details on the SCSR2 register and the PON and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data spaces. Flash EEPROM Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile. However, it has the advantage of "in-target" reprogrammability. The LF2401A incorporates one 8K 16-bit Flash EEPROM module in program space. The Flash module has two sectors that can be individually protected while erasing or programming. The sector size is partitioned as 4K/4K sectors. Unlike most discrete Flash memory, the LF2401A Flash does not require a dedicated state machine, because the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming, the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the algorithms and Flash code. This Flash requires 5 V for programming (at VCCP pin only) the array. The Flash runs at zero wait state while the device is powered at 3.3 V.
PRODUCT PREVIEW
IEEE Standard 1149.1-1990, IEEE Standard Test Access Port.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
boot ROM Boot ROM is a 256-word ROM mapped in program space 0000h-00FFh. This ROM will be enabled if the BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when: TRST RS TDI = = = 0 0 0
(In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected (TRST = 1), it can be achieved by writing a "0" into bit 3 of the SCSR2 register. The boot ROM has a generic bootloader to transfer code through the SCI port. The incoming code should disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not be enabled. The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows:
D If the SCITXD pin is pulled low, the PLL multiplier is set to 2. D If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default) D If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4.
Care should be taken such that a combination of CLKIN and the PLL multiplication factor should not result in a CPU clock speed of greater than 40 MHz, the maximum rated speed. Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI. Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A) for more details about the bootloader operation. Flash security The 2401A device has a security feature that prevents external access to Flash memory. This feature is useful in preventing unauthorized duplication of proprietary code resident on the Flash memory. If access to Flash contents are desired for debugging purposes, two actions need to be taken: 1. A "dummy" read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word "dummy" indicates that the destination address of this read is not relevant. If 40h-43h contain all zeros or ones, then Step 2 is not required. 2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h, 77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h, 41h, 42h, and 43h (of program memory space), respectively. The device becomes "unsecured" one cycle after the last instruction that unsecures the part.
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
PERIPHERALS
The integrated peripherals of the TMS320LF2401A are described in the following subsections:
D D D D D D
Event-manager module (EVA) Enhanced analog-to-digital converter (ADC) module Serial communications interface (SCI) module PLL-based clock module Digital I/O and shared pin functions Watchdog (WD) timer module
event manager module (EVA)
The event-manager module includes general-purpose (GP) timers, full-compare/PWM units, and a capture unit. Table 6 shows the module and signal names used. Table 6 also shows the features and functionality available for the event-manager module.
PRODUCT PREVIEW
EVA's peripheral register set starts at 7400h. The paragraphs in this section describe the function of the GP timers, the compare units, and the capture unit. Table 6. Module and Signal Names for EVA
EVENT MANAGER MODULES GP Timers MODULE Timer 1 Timer 2 Compare 1 Compare 2 Compare 3 Capture 1 SIGNAL -- T2PWM/T2CMP PWM1/2 PWM3/4 PWM5/6 CAP1
Compare Units Capture Unit
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
event manager module (EVA) (continued)
2401A DSP Core Data Bus ADDR Bus 16 16 16 EV Control Registers and Control Logic ADC Start of Conversion Reset INT2,3,4 Clock 3
16
GP Timer 1 Compare
16
GP Timer 1
Prescaler
CLKOUT (Internal)
16 SVPWM State Machine
T1CON[8,9,10]
PWM1 3 Deadband Units 3 Output Logic PWM6
16
Full-Compare Units
3
16
GP Timer 2 Compare
Output Logic
T2PWM
16
GP Timer 2
Prescaler
CLKOUT (Internal)
T2CON[8,9,10] 16
16
MUX
16 16
Capture Unit
CAP1
Figure 4. Event Manager A Block Diagram
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
general-purpose (GP) timers There are two GP timers. GP timer x (x = 1 or 2) includes:
D D D D D D D
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes A 16-bit timer-control register,TxCON, for reads or writes Internal input clock A programmable prescaler for internal clock input Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interrupts
PRODUCT PREVIEW
The GP timers can be operated independently or synchronized with each other. The compare register associated with GP timer 2 can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up / down-counting operations. An internal input clock with programmable prescaler is used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, and GP timer 2/1 for the capture unit. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed. full-compare units There are three full-compare units on the event manager (EVA). These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. programmable deadband generator The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values (from 0 to 16 s) can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register. PWM waveform generation Up to eight PWM waveforms (outputs) can be generated simultaneously by EVA: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
PWM characteristics Characteristics of the PWMs are as follows:
D D D D D D D D D
16-bit registers Programmable deadband for the PWM output pairs, from 0 to 12 s Minimum deadband width of 25 ns Change of the PWM carrier frequency for PWM frequency wobbling as needed Change of the PWM pulse widths within and after each PWM period as needed External-maskable power and drive-protection interrupts Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms Minimized CPU overhead using auto-reload of the compare and period registers The PWM pins are driven to a high-impedance state when the PDPINTA pin is driven low and after PDPINTA signal qualification. The status of the PDPINTA pin (after qualification) is reflected in bit 8 of the COMCONA register.
capture unit
D The capture unit includes the following features:
- - - - - One 16-bit capture control register, CAPCONA (R/W) One 16-bit capture FIFO status register, CAPFIFOA Selection of GP timer 1/2 as the time base One 16-bit 2-level-deep FIFO stack One capture input pin (CAP1). [The input is synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock.] User-specified transition (rising edge, falling edge, or both edges) detection One maskable interrupt flag
- -
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PRODUCT PREVIEW
The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stack when selected transitions are detected on the capture input pin, CAP1. The capture unit consists of three capture circuits.
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
input qualifier circuitry An input-qualifier circuitry qualifies the input signal to the CAP1, XINT1/2, ADCSOC, and PDPINTA pins in the 2401A device. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches.
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 5. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:
D D D D
10-bit ADC core with built-in S/H Fast conversion time (S/H + Conversion) of 500 ns 5-channel, muxed inputs Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be programmed to select any 1 of 5 input channels (i.e., two cascaded 8-state sequencers)
PRODUCT PREVIEW
D Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer D Sixteen result registers (individually addressable) to store conversion values
- The digital value of the input analog voltage is derived by: Digital Value + 1023 Input Analog Voltage * V REFLO V REFHI * V REFLO
NOTE: VREFLO is internally tied to VSSA ; VREFHI is internally tied to VCCA .
D Multiple triggers as sources for the start-of-conversion (SOC) sequence
- - - S/W - software immediate start EVA - Event manager A (multiple event sources within EVA) Ext - External pin (ADCSOC)
D Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS D Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize
conversions
D D D D
EVA triggers can operate independently in dual-sequencer mode Sample-and-hold (S/H) acquisition time window has separate prescale control Built-in calibration mode Built-in self-test mode
NOTE: The 2401A ADC module is identical to the LF2407A ADC module. However, only channels ADC0 through ADC4 are bonded out of the device. For this reason, the valid values for the CONVnn bit fields in the CHSELSEQn registers are from 0 to 4. Attempting to convert channels 5 through 15 would yield indeterminate results.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
enhanced analog-to-digital converter (ADC) module (continued)
The ADC module in the 2401A has been enhanced to provide flexible interface to the event manager (EVA). The ADC interface is built around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H + conversion). The ADC module has 5 channels to service EVA. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 5 shows the block diagram of the 2401A ADC module.
Analog MUX Result Registers Result Reg 0 ADCIN00 Result Reg 1 70A8h
ADCIN01 10-Bit ADC Module (500 ns) Result Reg 7 Result Reg 8 70AFh 70B0h
ADCIN02
ADCIN03
ADCIN04 Result Reg 15 70B7h
ADC Control Registers S/W EVA ADCSOC SOC Sequencer 1 Sequencer 2 SOC S/W
Figure 5. Block Diagram of the 2401A ADC Module To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCINn pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (such as VCCA and VSSA) from the digital supply.
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
serial communications interface (SCI) module
The 2401A device includes a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register. Features of the SCI module include:
D Two external pins:
- - SCITXD: SCI transmit-output pin SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
D Baud rate programmable to 64K different rates
- Up to 2500 Kbps at 40-MHz CPUCLK
D Data-word format
PRODUCT PREVIEW
- - - -
One start bit Data-word length programmable from one to eight bits Optional even/odd/no parity bit One or two stop bits
D D D D D
Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: idle-line and address bit Half- or full-duplex operation Double-buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. - - Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
D Separate enable bits for transmitter and receiver interrupts (except BRKDT) D NRZ (non-return-to-zero) format D Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register data is in the lower byte (7 - 0), and the upper byte (15 - 8) is read as zeros. Writing to the upper byte has no effect.
Figure 6 shows the SCI module block diagram.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
serial communications interface (SCI) module (continued)
SCITXBUF.7-0 Transmitter-Data Buffer Register 8 WUT TXSHF Register SCIHBAUD. 15 - 8 Baud Rate MSbyte Register SCILBAUD. 7 - 0 Baud Rate LSbyte Register SCI Priority Level 1 Level 5 Int. 0 Level 1 Int. SCI TX Priority SCIPRI.6 Level 5 Int. 1 TXENA SCICTL1.1 SCITXD SCITXD SCI TX Interrupt TXRDY TX INT ENA SCICTL2.7 TX EMPTY SCICTL2.6 SCICTL2.0
TXWAKE Frame Format and Mode Parity Even/Odd Enable SCICCR.6 SCICCR.5 SCICTL1.3 1
TXINT
External Connections
Internal Clock
0 Level 1 Int. SCI RX Priority SCIPRI.5
RXWAKE SCIRXST.1 RX ERR INT ENA SCICTL1.6
RXSHF Register
SCIRXD
SCIRXD
RXENA SCICTL1.0 8 SCI RX Interrupt RXRDY SCIRXST.6 BRKDT SCIRXST.5 RX/BK INT ENA SCICTL2.1 RXINT
RX Error SCIRXST.7 RX Error SCIRXST.4 - 2 FE OE PE
Receiver-Data Buffer Register SCIRXBUF.7-0
Figure 6. Serial Communications Interface (SCI) Module Block Diagram
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
PLL-based clock module
The 2401A has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different CPU clock rates. See Figure 7 for the PLL Clock Module Block Diagram and Table 7 for clock rates. The PLL-based clock module provides two modes of operation:
D Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
D External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the XTAL1/CLKIN pin.
XTAL1/CLKIN Cb1
Fin
PLL
CLKOUT
PRODUCT PREVIEW
RESONATOR/ CRYSTAL
XTAL OSC 3-bit PLL Select (SCSR1.[11:9])
XTAL2 Cb2
Figure 7. PLL Clock Module Block Diagram Table 7. PLL Clock Selection Through Bits (11- 9) in SCSR1 Register
CLK PS2 0 0 0 0 1 1 1 1 CLK PS1 0 0 1 1 0 0 1 1 CLK PS0 0 1 0 1 0 1 0 1 CLKOUT 4 x Fin 2 x Fin 1.33 x Fin 1 x Fin 0.8 x Fin 0.66 x Fin 0.57 x Fin 0.5 x Fin
Default multiplication factor after reset is (1,1,1), i.e., 0.5 x Fin.
CAUTION: The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN used should not force CLKOUT to exceed the maximum rated device speed. See the "Boot ROM" section for more details.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
external reference crystal clock option
The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown in Figure 8a. The crystal should be in fundamental operation and parallel resonant, with an effective series resistance of 30 -150 and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF.
external reference oscillator clock option
The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input pin unconnected as shown in Figure 8b.
XTAL1/CLKIN
XTAL2
XTAL1/CLKIN
XTAL2
Cb1 (see Note A)
Crystal (a)
Cb2 (see Note A)
External Clock Signal (Toggling 0 - 3.3 V) (b)
NC
Figure 8. Recommended Crystal / Clock Connection
low-power modes
The 2401A has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if it is reset, or, if it receives an interrupt request.
clock domains
All 2401A-based devices have two clock domains: 1. CPU clock domain - consists of the clock for most of the CPU logic 2. System clock domain - consists of the peripheral clock (which is derived from CLKOUT of the CPU) and the clock for the interrupt logic in the CPU. When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues to run. This mode is also known as IDLE1 mode. The 2401A CPU also contains support for a second IDLE mode, IDLE2. By asserting IDLE2 to the 2401A CPU, both the CPU clock domain and the system clock domain are stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the oscillator and WDCLK are also shut down when in IDLE2 mode. Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the IDLE instruction is executed (see Table 8). These bits are located in the System Control and Status Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A).
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PRODUCT PREVIEW
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range.
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
clock domains (continued)
Table 8. Low-Power Modes Summary
LOW-POWER MODE CPU running normally LPMx BITS SCSR1 [13:12] XX CPU CLOCK DOMAIN On SYSTEM CLOCK DOMAIN On WDCLK STATUS On PLL STATUS On OSC STATUS On FLASH POWER On EXIT CONDITION -- Peripheral Interrupt, External Interrupt, Reset, PDPINTA Wakeup Interrupts, External Interrupt, Reset, PDPINTA Reset, PDPINTA
IDLE1 - (LPM0)
00
Off
On
On
On
On
On
IDLE2 - (LPM1)
01
Off
Off
On
On
On
On
PRODUCT PREVIEW
HALT - (LPM2) [PLL/OSC power down]
1X
Off
Off
Off
Off
Off
Off
The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A).
other power-down options
2401A devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, and EVA. Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device. Depending on the application, these peripherals can be turned on/off to achieve low power. Refer to the SCSR1 register for details on the peripheral clock enable bits.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
digital I/O and shared pin functions
The 2401A has up to 13 general-purpose, bidirectional, digital I/O (GPIO) pins--most of which are shared between primary functions and I/O. Most I/O pins of the 2401A are shared with other functions. The digital I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
D Output Control Registers -- used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
D Data and Control Registers -- used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins The control structure for shared I/O pins is shown in Figure 9, where each pin has three bits that define its operation:
D Mux control bit -- this bit selects between the primary function (1) and I/O function (0) of the pin. D I/O direction bit -- if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1). is an input, data is read from this bit; if the direction selected is an output, data is written to this bit. The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
IOP Data Bit (Read/Write)
Primary Function Out
In
IOP DIR Bit 0 = Input 1 = Output
0
1
MUX Control Bit 0 = I/O Function 1 = Primary Function
Pullup or Pulldown Primary Function or I/O Pin Pin
Figure 9. Shared Pin Configuration A summary of shared pin configurations and associated bits is shown in Table 9.
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D I/O data bit -- if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
description of shared I/O pins (continued) Table 9. Shared Pin Configurations
PIN FUNCTION SELECTED (MCA.n = 1) Primary Function (MCA.n = 0) Secondary Function IOPA0 IOPA1 IOPA2 IOPA3 IOPA4 IOPA5 IOPA6 XINT2/ADCSOC/ CAP1/IOPA7 XINT1/IOPB0 IOPB1 IOPB2 IOPB3 IOPB4 OPB5 MUX CONTROL REGISTER (name.bit #) MUX CONTROL VALUE AT RESET (MCRx.n) I/O PORT DATA AND DIRECTION REGISTER PORT A PDPINTA PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 CLKOUT MCRA.0 MCRA.1 MCRA.2 MCRA.3 MCRA.4 MCRA.5 MCRA.6 MCRA.7 0 0 0 0 0 0 0 0 PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PADATDIR PORT B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA BIT NO. DIR BIT NO.
PRODUCT PREVIEW
T2PWM IOPB1 IOPB2 SCITXD SCIRXD OPB5 - -
MCRA.8 MCRA.9 MCRA.10 MCRA.11 MCRA.12 MCRA.13 MCRA.14 MCRA.15
0 0 0 0 0 0 0 0
PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR PBDATDIR
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14
15 Valid only if the I/O function is selected on the pin If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from. If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
digital I/O control registers Table 10 lists the registers available in the digital I/O module. As with other 2401A peripherals, these registers are memory-mapped to the data space. Table 10. Addresses of Digital I/O Control Registers
ADDRESS 7090h 7098h 709Ah REGISTER MCRA PADATDIR PBDATDIR NAME I/O mux control register A I/O port A data and direction register I/O port B data and direction register
CAUTION: The bit definitions of the MCRA, PADATDIR, and PBDATDIR registers are not compatible with those of other 24x/240x devices.
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TMS320LF2401A DSP CONTROLLER
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watchdog (WD) timer module
The 2401A device includes a watchdog (WD) timer module. The WD function of this module monitors software and hardware operation by generating a system reset if it is not periodically serviced by software by having the correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up sequence. See Figure 10 for a block diagram of the WD module. The WD module features include the following: D WD Timer - Seven different WD overflow rates - A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and generates a system reset if an incorrect value is written to the register - WD check bits that initiate a system reset if an incorrect value is written to the WD control register (WDCR) D Automatic activation of the WD timer, once system reset is released - Three WD control registers located in control register frame beginning at address 7020h.
Table 11 shows the different WD overflow (time-out) selections. Figure 10 shows the WD block diagram. The watchdog can be disabled in software by writing `1' to bit 6 of the WDCR register (WDCR.6) while bit 5 of the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent to the WDDIS pin of the TMS320F243/241 devices. Table 11. WD Overflow (Time-out) Selections
WD PRESCALE SELECT BITS WDPS2 0 0 0 1 1 1 1 WDCLK = CLKOUT/512 X = Don't care WDPS1 0 1 1 0 0 1 1 WDPS0 X 0 1 0 1 0 1 WDCLK DIVIDER 1 2 4 8 16 32 64 WATCHDOG CLOCK RATE FREQUENCY (Hz) WDCLK/1 WDCLK/2 WDCLK/4 WDCLK/8 WDCLK/16 WDCLK/32 WDCLK/64
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PRODUCT PREVIEW
NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte is read as zeros. Writing to the upper byte has no effect.
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
watchdog (WD) timer module (continued)
CLKOUT 3-bit Prescaler CLKIN
/ 512 6-Bit FreeRunning Counter /64 /32 /16 /8 /4 /2
PLL
WDCLK System Reset
On-Chip Oscillator or External Clock
CLR
000 001 010 WDPS WDCR.2 - 0 210 WDCR.6 WDDIS 111 WDCNTR.7 - 0 8-Bit Watchdog Counter CLR One-Cycle Delay WDFLAG WDCR.7 PS/257 Reset Flag 011 100 101 110
PRODUCT PREVIEW
WDKEY.7 - 0 Bad Key Watchdog Reset Key Register 55 + AA Detector Good Key WDCHK2-0 WDCR.5 - 3 Bad WDCR Key 3 3 System Reset 101 (Constant Value) Writing to bits WDCR.5 - 3 with anything but the correct pattern (101) generates a system reset.
System Reset Request
Figure 10. Block Diagram of the WD Module
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
development support
Texas Instruments (TI) offers an extensive line of development tools for the 240x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of 240x-based applications: Software Development Tools: Assembler/linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler Hardware Development Tools: Emulator XDS510 (supports x24x multiprocessor system debug) TMS320LF2407 EVM (Evaluation module for 2407 DSP) The TMS320 DSP Development Support Reference Guide (literature number SPRU011) contains information about development support products for all TMS320 DSP family member devices, including documentation. Refer to this document for further information about TMS320 DSP documentation or any other TMS320 DSP support products from Texas Instruments. There is also an additional document, the TMS320 Third-Party Support Reference Guide (literature number SPRU052), which contains information from other companies in the industry regarding products related to the TMS320 DSPs . To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924. See Table 12 and Table 13 for complete listings of development support tools for the 240x. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Table 12. Development Support Tools
DEVELOPMENT TOOL Assembler/Linker C Compiler/Assembler/Linker LF2407 eZdsp Code Composer 4.12, Code Generation 7.0 XDS510XL Board (ISA card), w/JTAG cable XDS510PP Pod (Parallel Port) w/JTAG cable PLATFORM Software - Code Generation Tools PC, Windows 95 PC, Windows 95 Software - Emulation Debug Tools PC PC Hardware - Emulation Debug Tools PC PC TMDS00510 TMDS00510PP TMDS3P761119 TMDS324012xx TMDS3242850-02 TMDS3242855-02 PART NUMBER
PC is a trademark of International Business Machines Corp. Windows is a registered trademark of Microsoft Corporation. XDS510XL and XDS510PP are trademarks of Texas Instruments.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
development support (continued)
Table 13. TMS320x24x-Specific Development Tools
DEVELOPMENT TOOL TMS320LF2407A EVM TMS320F240 EVM TMS320F243 EVM PLATFORM Hardware - Evaluation/Starter Kits PC, Windows 95, Windows 98 PC PC, Windows 95 TMDX3P701016 TMDX326P124X TMDS3P604030 PART NUMBER
device and development support tool nomenclature To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). This development flow is defined below. Support tool development evolutionary flow:
PRODUCT PREVIEW
TMDX TMDS
Development support product that has not completed TI's internal qualification testing Fully qualified development support product
TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development support tools have been fully characterized, and the quality and reliability of the device have been fully demonstrated. TI's standard warranty applies.
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TMS320LF2401A DSP CONTROLLER
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device and development support tool nomenclature (continued) TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, VF) and temperature range (for example, S). Figure 11 provides a legend for reading the complete TMS320LF2401A device name. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS 320 LF 2401A PREFIX TMX = experimental device TMP = prototype device TMS = qualified device VF A
TEMPERATURE RANGES A = -40C to 85C S = -40C to 125C
DEVICE FAMILY 320 = TMS320 DSP Family
PACKAGE TYPE VF = 32-pin LQFP
TECHNOLOGY LC = Low-voltage CMOS (3.3 V) LF = Flash EEPROM (3.3 V)
LQFP =
Low-Profile Quad Flatpack
Figure 11. TMS320LF2401A Device Nomenclature
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PRODUCT PREVIEW
DEVICE 2401A
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
documentation support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's guides for all devices and development support tools; and hardware and software applications. Useful reference documentation includes:
D User Guides
- - TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A) TMS320C240 DSP Controllers CPU, System, and Instruction Set Reference Guide (literature number SPRU160)
D Data Sheets
- - TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP Controllers (literature number SPRS094) TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers (literature number SPRS145)
PRODUCT PREVIEW
D Application Reports
- 3.3V DSP for Digital Motor Control (literature number SPRA550) A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com. To send comments regarding the TMS320LF2401A data sheet (literature number SPRS161), use the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site. NOTE: The LF2401A device has reduced peripheral functionality compared to other 24x/240x devices. While peripherals such as SPI and CAN are absent on the LF2401A, peripherals such as EV and ADC have reduced functionality. For example, in the case of EV, there is no QEP unit and the Capture unit has only one capture pin (as opposed to three or six pins in other devices). The ADC has only five input channels (as opposed to eight or sixteen channels in other devices). For these reasons, some bits that are valid in other 24x/240x devices are not applicable in the LF2401A. The registers and their valid bits are described in Table 15, LF2401A DSP Peripheral Register Description. For a description of those registers and bits that are valid, refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A). Any exceptions to SPRU357A has been described in the respective peripheral sections in this data sheet.
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absolute maximum ratings over operating free-air temperature ranges (unless otherwise noted)
Supply voltage range, VDD, VDDO, and VCCA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V VCCP range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5.5 V Input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Clamp current stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VDD/VDDO VSS VCCA VCCP fCLKOUT VIH VIL IOH Supply voltage Supply ground ADC supply voltage Flash programming supply voltage Device clock frequency (system clock) High level input voltage High-level Low-level Low level input voltage High level output High-level out ut source current, VOH = 2.4 V All inputs All inputs Output pins Group 1 Output pins Group 2 Output pins Group 3 Output pins Group 1 IOL Low level output Low-level out ut sink current, VOL = VOL MAX A version TA Free-air Free air temperature S version Output pins Group 2 Output pins Group 3 - 40 - 40 VDDO = VDD 0.3 V 3 0 3 4.75 4 2 0.8 08 -2 -4 -8 2 4 8 85 125 NOM 3.3 0 3.3 5 MAX 3.6 0 3.6 5.25 40 UNIT V V V MHz V V mA mA mA mA mA mA C C cycles V
TJ Junction temperature - 40 25 150 Nf Flash endurance for the array (Write/erase cycles) - 40C to 85C 10K Refer to the mechanical data package page for thermal resistance values, JA (junction-to-ambient) and JC (junction-to-case). VCCA should not exceed VDD by 0.3 V. Primary signals and their groupings: Group 1: PDPINTA/IOPA0, T2PWM, PWM1-PWM6 (IOPA1-IOPA6), IOPB1, OPB5, TMS/XF Group 2: SCITXD/IOPB3, SCIRXD/IOPB4, TDO/IOPB2 Group 3: CAP1
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
electrical characteristics over recommended operating free-air temperature ranges (unless otherwise noted)
PARAMETER VOH VOL IIL IIH IOZ Ci Co High-level High level output voltage Low-level output voltage With pullup Input current (low level) Input current (high level) With pulldown With pullup With pulldown VDD = 3 3 V, VIN = VDD 3.3 V VO = VDD or 0 V 2 3 9 16 Output current, high-impedance state (off-state) Input capacitance Output capacitance VDD = 3 3 V, VIN = 0 V 3.3 V TEST CONDITIONS VDD = 3.0 V, IOH = IOHMAX All outputs at 50 A IOL = IOLMAX -9 -16 MIN 2.4 VDDO - 0.2 0.4 -25 2 2 25 2 V V A A A A A pF pF TYP MAX UNIT
current consumption by power-supply pins over recommended operating free-air temperature ranges at 40-MHz CLOCKOUT
PRODUCT PREVIEW
PARAMETER IDD Operational Current
TEST CONDITIONS Clock to all peripherals is enabled. CPU is running a simple loop code and no I/O pins are switching.
MIN
TYP 60 5
MAX 95 15
UNIT mA mA
ICCA ADC module current IDD is the current flowing into the VDD and VDDO pins.
current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT
PARAMETER IDD ICCA IDD ICCA IDD Operational Current ADC module current Operational Current ADC module current Operational Current LPM2 Clock to all peripherals is disabled disabled. 0 0 LPM1 LPM0 MODE TEST CONDITIONS Clock to all peripherals is enabled. eri herals No I/O pins are switching. Clock to all peripherals is disabled. eri herals No I/O pins are switching. MIN TYP 72 0.2 48 0 200 MAX 96 1 72 0 UNIT mA mA mA mA A mA
ICCA ADC module current IDD is the current flowing into the VDD and VDDO pins.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
current consumption graphs
100 90 80 Current (mA) IDD 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 CLKOUT Frequency (MHz) Figure 12. LF2401A Typical Current Consumption (With Peripheral Clocks Enabled)
reducing current consumption
240x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 14 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals. Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A) for further information on how to turn off the clock to the peripherals. Table 14. Typical Current Consumption by Various Peripherals (at 40 MHz)
PERIPHERAL MODULE EVA ADC SCI ADC current shown is at 30 MHz. CURRENT REDUCTION (mA) 6.1 2.8 1.9
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
PARAMETER MEASUREMENT INFORMATION
IOL Tester Pin Electronics VLOAD 50 CT Output Under Test
IOH Where: IOL IOH VLOAD CT = = = = 2 mA (all outputs) 300 A (all outputs) 1.5 V 50-pF typical load-circuit capacitance
Figure 13. Test Load Circuit
signal transition levels
PRODUCT PREVIEW
The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.8 V. Figure 14 shows output levels.
2.4 V (VOH) 80% 20% 0.4 V (VOL)
Figure 14. Output Levels Output transition times are specified as follows: D For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower. D For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage range and higher and the level at which the output is said to be high is 80% of the total voltage range and higher. Figure 15 shows the input levels.
2.0 V (VIH) 90% 10% 0.8 V (VIL)
Figure 15. Input Levels Input transition times are specified as follows: D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher.
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PARAMETER MEASUREMENT INFORMATION timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CI CO RS INT XTAL1 CLKOUT RESET pin RS XINT1, XINT2 Letters and symbols and their meanings: H L V X Z High Low Valid Unknown, changing, or don't care level High impedance
Lowercase subscripts and their meanings: a c d f h r su t v w access time cycle time (period) delay time fall time hold time rise time setup time transition time valid time pulse duration (width)
general notes on timing parameters
All output signals from the 2401A device (including CLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
external reference crystal/clock with PLL circuit enabled timings with the PLL circuit enabled
PARAMETER Resonator fx In ut Input clock frequency Crystal CLKIN MIN 4 4 4 MAX 13 20 20 MHz UNIT
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 16)
PARAMETER tc(CO) tf(CO) tr(CO) tw(COL) tw(COH) Cycle time, CLKOUT Fall time, CLKOUT Rise time, CLKOUT Pulse duration, CLKOUT low Pulse duration, CLKOUT high H -3 H -3 PLL MODE x4 mode MIN 33 4 4 H H H +3 H +3 TYP MAX UNIT ns ns ns ns ns ns
PRODUCT PREVIEW
tt 4096tc(Cl) Transition time, PLL synchronized after RS pin high Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
timing requirements (see Figure 16)
MIN tc(Cl) tf(Cl) tr(Cl) tw(CIL) tw(CIH) Cycle time, XTAL1/CLKIN Fall time, XTAL1/CLKIN Rise time, XTAL1/CLKIN Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl) Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl) tc(CI) tw(CIH) tf(Cl) tw(CIL) XTAL1/CLKIN tw(COH) tc(CO) CLKOUT tw(COL) tr(CO) tf(CO) tr(Cl) 40 40 MAX 250 5 5 60 60 UNIT ns ns ns % %
Figure 16. CLKIN-to-CLKOUT Timing with PLL and External Clock in x4 Mode
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
RS timings timing requirements for a reset [H = 0.5tc(CO)] (see Figure 17 and Figure 18)
MIN tw(RSL) tw(RSL2) tp td(EX) VDD/VDDO
tp tw(RSL) td(EX)
NOM
MAX
UNIT cycles cycles
Pulse duration, stable CLKIN to RS high Pulse duration, RS low PLL lock-up time Delay time, reset vector executed after PLL lock time
8tc(CI) 8tc(CI) 4096tc(CI) 36H
cycles ns
RS
CLKIN
XTAL1
tOSCST
TDI
BOOT_EN
TDI/OPB5
CLKOUT
I/Os
Hi-Z
Code-Dependent
XTAL1 refers to internal oscillator clock if on-chip oscillator is used. tOSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the "TDI/OPB5" phase, this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low). Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 17. Power-on Reset
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
RS timings (continued)
td(EX) tw(RSL2) tp
RS
CLKIN
XTAL1
TDI
BOOT_EN
TDI/OPB5
PRODUCT PREVIEW
CLKOUT
I/Os
Hi-Z
Code-Dependent
XTAL1 refers to internal oscillator clock if on-chip oscillator is used. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the "TDI/OPB5" phase, this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low). Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 18. Warm Reset
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
RS timings (continued) switching characteristics over recommended operating conditions for a reset [H = 0.5tc(CO)] (see Figure 19)
PARAMETER tw(RSL1) td(EX) Pulse duration, RS low Delay time, reset vector executed after PLL lock time MIN 128tc(CI) 36H 4096tc(CI) MAX UNIT ns ns ns
tp PLL lock time (input cycles) The parameter tw(RSL1) refers to the time RS is an output.
td(EX) tw(RSL1) tp
RS
CLKIN
XTAL1
TDI
BOOT_EN
TDI/OPB5
CLKOUT
I/Os
Hi-Z
Code-Dependent
XTAL1 refers to internal oscillator clock if on-chip oscillator is used. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the "TDI/OPB5" phase, this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low). Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 19. Watchdog Initiated Reset
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
low-power mode timings switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 20, Figure 21, and Figure 22)
PARAMETER td(WAKE-A) td(IDLE-COH) td(WAKE-OSC) td(IDLE-OSC) td(EX) Delay time, CLKOUT switching to program execution resume Delay time, Idle instruction executed to CLKOUT high Delay time, wakeup interrupt asserted to oscillator running Delay time, Idle instruction executed to oscillator power off LOW-POWER MODES IDLE1 IDLE2 IDLE2 LPM0 LPM1 LPM1 MIN TYP 12 x tc(CO) 15 x tc(CO) 4tc(CO) OSC start-up and PLL lock time 4tc(CO) 36H td(WAKE-A) MAX UNIT ns ns
ms
HALT {PLL/OSC power down} d }
LPM2
ns ns
Delay time, reset vector executed after RS high
PRODUCT PREVIEW
A0-A15
CLKOUT
WAKE INT In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. WAKE INT can be any valid interrupt or RESET.
Figure 20. IDLE1 Entry and Exit Timing - LPM0
td(IDLE-COH) A0-A15 CLKOUT
WAKE INT td(WAKE-A) In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. WAKE INT can be any valid interrupt or RESET.
Figure 21. IDLE2 Entry and Exit Timing - LPM1
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
low-power mode timings (continued)
td(EX) A0-A15 td(IDLE-OSC) td(IDLE-COH) CLKOUT td(WAKE-OSC)
RESET
In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 22. HALT Mode - LPM2
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PRODUCT PREVIEW
AA
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
LPM2 wakeup timings switching characteristics over recommended operating conditions (see Figure 23)
PARAMETER td(PDP-PWM)HZ td(INT) Delay time, PDPINTA low to PWM high-impedance state Delay time, INT low/high to interrupt-vector fetch 10tc(CO) MIN MAX 12 UNIT ns ns
timing requirements (see Figure 23)
MIN if bit 6 of SCSR2 = 0 tw(PDP-WAKE) (PDP WAKE) tp Pulse duration PDPINTA input low duration, PLL lock-up time if bit 6 of SCSR2 = 1 6tc(CO) 12tc(CO) 4096tc(CI) MAX UNIT ns cycles
PRODUCT PREVIEW
XTAL1
Oscillator Disabled tOSC tp
CLKIN
CLKOUT
tw(PDP-WAKE) PDPINTA
td(PDP-PWM)HZ PWM
td(INT) CPU Status CPU IDLE State (LPM2) Interrupt Vector or Next Instruction#
tOSC is the oscillator start-up time. CLKOUT frequency after LPM2 wakeup will be the same as that upon entering LPM2 (x4 shown as an example). Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. PDPINTA interrupt vector, if PDPINTA interrupt is enabled. # If PDPINTA interrupt is disabled.
Figure 23. LPM2 Wakeup Using PDPINTA
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
XF timings switching characteristics over recommended operating conditions (see Figure 24)
PARAMETER td(XF) Delay time, CLKOUT high to XF high/low MIN -3 MAX 7 UNIT ns
CLKOUT
td(XF)
XF
Figure 24. XF Timing
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
TIMING EVENT MANAGER INTERFACE PWM timings
PWM refers to all PWM outputs on EVA.
switching characteristics over recommended operating conditions for PWM timing [H = 0.5tc(CO)] (see Figure 25)
PARAMETER tw(PWM) Pulse duration, PWMx output high/low MIN 2H+5 15 MAX UNIT ns ns
td(PWM)CO Delay time, CLKOUT low to PWMx output switching PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.
CLKOUT
PRODUCT PREVIEW
td(PWM)CO tw(PWM) PWMx
Figure 25. PWM Output Timing
56
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
capture timings timing requirements (see Figure 26)
MIN if bit 6 of SCSR2 = 0 tw(CAP) (CAP) Pulse duration CAP1 input low/high duration, if bit 6 of SCSR2 = 1 6tc(CO) 12tc(CO) MAX UNIT ns
CLKOUT
tw(CAP) CAP1
Figure 26. Capture Input Timing
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
interrupt timings
INT refers to XINT1 and XINT2.
switching characteristics over recommended operating conditions (see Figure 27)
PARAMETER td(PDP-PWM)HZ td(INT) Delay time, PDPINTA low to PWM high-impedance state Delay time, INT low/high to interrupt-vector fetch 10tc(CO) MIN MAX 12 UNIT ns ns
timing requirements (see Figure 27)
MIN if bit 6 of SCSR2 = 0 tw(INT) (INT) Pulse duration INT input low/high duration, if bit 6 of SCSR2 = 1 if bit 6 of SCSR2 = 0 tw(PDP) (PDP) Pulse duration, PDPINTA input low duration if bit 6 of SCSR2 = 1 6tc(CO) 12tc(CO) 6tc(CO) 12tc(CO) MAX UNIT ns
ns
PRODUCT PREVIEW
CLKOUT
tw(PDP) PDPINTA td(PDP-PWM)HZ PWM
tw(INT) XINT1, XINT2 td(INT) Interrupt Vector
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTA is taken high depends on the state of the FCOMPOE bit.
Figure 27. Power Drive Protection Interrupt Timing
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
general-purpose input/output timings switching characteristics over recommended operating conditions (see Figure 28)
PARAMETER td(GPO)CO tr(GPO) tf(GPO) Delay time, Dela time CLKOUT lo to GPIO low/high low lo /high Rise time, GPIO switching low to high Fall time, GPIO switching high to low All GPIOs All GPIOs All GPIOs MIN MAX 9 8 6 UNIT ns ns ns
timing requirements [H = 0.5tc(CO)] (see Figure 29)
MIN tw(GPI) Pulse duration, GPI high/low 2H+15 MAX UNIT ns
CLKOUT
td(GPO)CO
GPIO tr(GPO)
tf(GPO)
Figure 28. General-Purpose Output Timing
CLKOUT
tw(GPI) GPIO
Figure 29. General-Purpose Input Timing
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA. The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic circuitry that can be present on VSS and VCC from coupling into the ADC analog stage. All ADC specifications are given with respect to VSSA unless otherwise noted. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-bit (1024 values) Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . 000h to 3FFh (000h for VI VSSA; 3FFh for VI VCCA) Conversion time (including sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
recommended operating conditions
MIN VCCA VSSA Analog supply voltage Analog ground 3.0 NOM 3.3 0 VREFHI MAX 3.6 UNIT V V V
VAI Analog input voltage, ADCIN00-ADCIN07 VREFLO VCCA and VSSA must be stable, within 1/2 LSB of the required resolution, during the entire conversion time.
PRODUCT PREVIEW
ADC operating frequency
MIN ADC operating frequency 4 MAX 40 UNIT MHz
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
operating characteristics over recommended operating condition ranges
PARAMETER VCCA = 3.3 V ICCA IADCIN Cai EDNL EINL td(PU) Analog supply current Analog input leakage Analog input capacitance Differential nonlinearity error Typical ca acitive load on Ty ical capacitive analog input pin Non-sampling Sampling 10 30 "2 "2 pF LSB VCCA = VREFHI = 3.3 V PLL or OSC power down DESCRIPTION MIN TYP 10 MAX 15 1 1 UNIT mA mA mA
Difference between the actual step width and the ideal value Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error Time to stabilize analog stage after power-up Analog input source impedance needed for conversions to remain within specifications at min tw(SH)
Integral nonlinearity error Delay time, power-up to ADC valid Analog input source impedance
LSB ms
10
ZAI
10
Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
internal ADC module timings (see Figure 30)
MIN tc(AD) tw(SHC) tw(SH) tw(C) td(SOC-SH) td(EOC) Cycle time, ADC prescaled clock Pulse duration, total sample/hold and conversion time Pulse duration, sample and hold time Pulse duration, total conversion time Delay time, start of conversion to beginning of sample and hold Delay time, end of conversion to data loaded into result register 2tc(AD) 10tc(AD) 3tc(CO) 2tc(CO) MAX 33.3 500 32tc(AD) UNIT ns ns ns ns ns ns
td(ADCINT) Delay time, ADC flag to ADC interrupt 2tc(CO) ns The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357A) for more details. The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC) . Can be varied by ACQ Prescalar bits in the ADCCTRL1 register tc(AD) Bit Converted ADC Clock 9 8 7 6 5 4 3 2 1 0
PRODUCT PREVIEW
EOC/Convert
Internal Start/ Sample Hold td(SOC-SH) Start of Convert tw(SHC)
XFR to RESULTn
62
AAAAAAAAAAAAAAAAAAAAA AAAAA AA
tw(C) tw(SH) td(EOC) td(ADCINT)
Analog Input
Figure 30. Analog-to-Digital Internal Module Timing
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
Flash parameters @40 MHz CLOCKOUT
PARAMETER Clear/Programming time Erase time ICCP (VCCP pin current) Time/Word (16-bit) Time/4K Sector Time/4K Sector Indicates the typical/maximum current consumption during the Clear-Erase-Program (C-E-P) cycle MIN TYP 30 130 350 5 15 MAX UNIT s ms ms mA
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values specified are when VDD = 3.3 V and VCCP = 5 V, and any deviation from these values could affect the timing parameters. Aging and process variance could also impact the timing parameters.
migrating from other 240xA devices to LF2401A
This section outlines some of the issues to be considered while migrating a design from the 240xA family to the LF2401A. The LF2401A shares the same CPU core (and hence, the same instruction set) as the 240xA. Furthermore, the peripherals implemented on the LF2401A are a subset of those found in the 240xA family. However, some features of a particular peripheral may not be present on the 2401A. This must be taken into consideration while porting code to the LF2401A. Other issues to be considered for migration are as follows. PLL The PLL used in the LF2401A is different than the one used in the 240xA family. The LF2401A PLL does not need the external loop-filter components. on-chip bootloader Boot ROM is a 256-word ROM mapped in program space 0000h-00FFh. This ROM will be enabled if the BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when: TRST RS TDI = = = 0 0 0
(In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected (TRST = 1), it can be achieved by writing a "0" into bit 3 of the SCSR2 register. GPIO The multiplexing scheme of the GPIO pins with other functional pins is different in the LF2401A. Because of this, the bit assignments for the MCRA, PADATDIR, and PBDATDIR registers of the LF2401A is not compatible with the bit assignments of the 240xA family.
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PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
EV The Event Manager of the LF2401A has reduced functionality when compared to that of the 240xA family. Following are the important differences:
D D D D D
There is no QEP unit. There is only one "Capture" input (CAP1). Although Timer 1 is present, there is no compare output pin (T1CMP/T1PWM). There is no provision to feed an external clock to the timers. There is no external direction control pin for the timers.
Due to these differences, some of the bits in the EV registers are not applicable in the LF2401A and are shaded gray. Refer to Table 15, LF2401A DSP Peripheral Register Description, for more details. ADC The LF2401A ADC has only five input channels as compared to eight or sixteen channels in the 240xA family. Therefore, the 4-bit fields in the CHSELSEQn registers should be programmed with values from 0-4 only.
PRODUCT PREVIEW
The LF2401A ADC does not have dedicated VREFHI and VREFLO pins. Instead, the VCCA and VSSA pins provide the necessary reference. pins The following pins, which are available in other 240xA devices, have been internally tied as indicated: CAP2, CAP3 - low TDIRA TCLKINA BIO - low - low - high
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description
Table 15 is a collection of all the programmable registers of the LF2401A and is provided as a quick reference. Table 15. LF2401A DSP Peripheral Register Description
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
DATA MEMORY SPACE CPU STATUS REGISTERS ARP DP(7) 1 -- -- -- -- IRQ0.15 IRQ0.7 IRQ1.15 IRQ1.7 IRQ2.15 IRQ2.7 IAK0.15 IAK0.7 IAK1.15 IAK1.7 IAK2.15 IAK2.7 -- ADC CLKEN -- 07019h -- DP(6) ARB 1 -- -- -- -- IRQ0.14 IRQ0.6 IRQ1.14 IRQ1.6 IRQ2.14 IRQ2.6 IAK0.14 IAK0.6 IAK1.14 IAK1.6 IAK2.14 IAK2.6 CLKSRC SCI CLKEN -- I/P QUALIFIER CLOCKS 1 -- INT6 MASK -- INT6 FLAG IRQ0.13 IRQ0.5 IRQ1.13 IRQ1.5 IRQ2.13 IRQ2.5 IAK0.13 IAK0.5 IAK1.13 IAK1.5 IAK2.13 IAK2.5 LPM1 SPI CLKEN -- WD OVERRIDE DP(5) OV DP(4) CNF XF -- INT5 MASK -- INT5 FLAG IRQ0.12 IRQ0.4 IRQ1.12 IRQ1.4 IRQ2.12 IRQ2.4 Illegal IAK0.12 IAK0.4 IAK1.12 IAK1.4 IAK2.12 IAK2.4 Illegal LPM0 CAN CLKEN -- XMIF HI Z CLK PS2 EVB CLKEN -- BOOT_EN CLK PS1 EVA CLKEN -- MP/MC CLK PS0 -- -- DON -- ILLADR -- PON SCSR2 SCSR1 IAK0.11 IAK0.3 IAK1.11 IAK1.3 IAK2.11 IAK2.3 IAK0.10 IAK0.2 IAK1.10 IAK1.2 IAK2.10 IAK2.2 IAK0.9 IAK0.1 IAK1.9 IAK1.1 IAK2.9 IAK2.1 IAK0.8 IAK0.0 IAK1.8 IAK1.0 IAK2.8 IAK2.0 PIACKR0 PIACKR1 PIACKR2 Reserved -- INT4 FLAG IRQ0.11 IRQ0.3 IRQ1.11 IRQ1.3 IRQ2.11 IRQ2.3 -- INT3 FLAG IRQ0.10 IRQ0.2 IRQ1.10 IRQ1.2 IRQ2.10 IRQ2.2 -- INT2 FLAG IRQ0.9 IRQ0.1 IRQ1.9 IRQ1.1 IRQ2.9 IRQ2.1 -- INT1 FLAG IRQ0.8 IRQ0.0 IRQ1.8 IRQ1.0 IRQ2.8 IRQ2.0 OVM DP(3) TC 1 -- INT4 MASK 1 DP(2) SXM 1 -- INT3 MASK -- INT2 MASK INTM DP(1) C PM -- INT1 MASK DP(8) DP(0) 1 ST0 ST1
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS 00004h 00005h 00006h IMR GREG IFR
SYSTEM REGISTERS 07010h 07011h 07012h 07013h 07014h 07015h 07016h 07017h 07018h PIRQR0 PIRQR1 PIRQR2
0701Ah to 0701Bh 0701Ch 0701Dh 0701Eh 0701Fh V15 V7 V14 V6 V13 V5 V12 V4 DIN15 DIN7 DIN14 DIN6 DIN13 DIN5 DIN12 DIN4
Illegal DIN11 DIN3 Illegal V11 V3 Illegal These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. V10 V2 V9 V1 V8 V0 PIVR DIN10 DIN2 DIN9 DIN1 DIN8 DIN0
DINR
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description (continued)
Table 15. LF2401A DSP Peripheral Register Description (Continued)
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
WD CONTROL REGISTERS 07020h to 07022h 07023h 07024h 07025h 07026h to 07028h 07029h 0702Ah to 0703Fh WDFLAG WDDIS WDCHK2 WDCHK1 D7 D6 D5 D4 Illegal WDCHK0 Illegal WDPS2 WDPS1 WDPS0 WDCR D7 D6 D5 D4 Illegal D3 D2 D1 D0 WDKEY Illegal D3 D2 D1 D0 WDCNTR
PRODUCT PREVIEW
07040h to 0704Fh
Reserved SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
07050h 07051h 07052h 07053h 07054h 07055h 07056h 07057h 07058h 07059h 0705Ah to 0705Eh 0705Fh 07060h to 0706Fh
STOP BITS -- BAUD15 (MSB) BAUD7 TXRDY RX ERROR ERXDT7 RXDT7
EVEN/ODD PARITY RX ERR INT ENA BAUD14 BAUD6 TX EMPTY RXRDY ERXDT6 RXDT6
PARITY ENABLE SW RESET BAUD13 BAUD5 -- BRKDT ERXDT5 RXDT5
LOOP BACK ENA -- BAUD12 BAUD4 -- FE ERXDT4 RXDT4
ADDR/IDLE MODE TXWAKE BAUD11 BAUD3 -- OE ERXDT3 RXDT3 Illegal
SCI CHAR2 SLEEP BAUD10 BAUD2 -- PE ERXDT2 RXDT2
SCI CHAR1 TXENA BAUD9 BAUD1 RX/BK INT ENA RXWAKE ERXDT1 RXDT1
SCI CHAR0 RXENA BAUD8 BAUD0 (LSB) TX INT ENA -- ERXDT0 RXDT0
SCICCR SCICTL1 SCIHBAUD SCILBAUD SCICTL2 SCIRXST SCIRXEMU SCIRXBUF
TXDT7
TXDT6
TXDT5
TXDT4 Illegal
TXDT3
TXDT2
TXDT1
TXDT0
SCITXBUF
--
SCITX PRIORITY
SCIRX PRIORITY
SCI SOFT Illegal
SCI FREE
--
--
--
SCIPRI
These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the correa licable eri heral sponding pins have not been bonded out of the device.
66
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description (continued)
Table 15. LF2401A DSP Peripheral Register Description (Continued)
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
EXTERNAL INTERRUPT CONTROL REGISTERS XINT1 FLAG 07070h -- XINT2 FLAG 07071h -- 07072h to 0708Fh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- XINT1 POLARITY -- XINT2 POLARITY -- XINT1 PRIORITY -- XINT2 PRIORITY -- XINT1 ENA -- XINT2 ENA XINT2CR XINT1CR
Illegal DIGITAL I/O CONTROL REGISTERS MCRA.15 MCRA.14 MCRA.6 MCRA.13 MCRA.5 MCRA.12 MCRA.4 MCRA.11 MCRA.3 Illegal MCRB.15 MCRB.14 MCRB.6 MCRB.13 MCRB.5 MCRB.12 MCRB.4 MCRB.11 MCRB.3 Illegal MCRC.15 MCRC.14 MCRC.6 E6DIR IOPE6 F6DIR IOPF6 MCRC.13 MCRC.5 E5DIR IOPE5 F5DIR IOPF5 MCRC.12 MCRC.4 E4DIR IOPE4 F4DIR IOPF4 Illegal A7DIR A6DIR IOPA6 A5DIR IOPA5 A4DIR IOPA4 Illegal B7DIR B6DIR IOPB6 B5DIR IOPB5 B4DIR IOPB4 Illegal C7DIR C6DIR IOPC6 C5DIR IOPC5 C4DIR IOPC4 Illegal D7DIR D6DIR IOPD6 D5DIR IOPD5 D4DIR IOPD4 Illegal These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the correa licable eri heral sponding pins have not been bonded out of the device. D3DIR IOPD3 D2DIR IOPD2 D1DIR IOPD1 D0DIR IOPD0 PDDATDIR C3DIR IOPC3 C2DIR IOPC2 C1DIR IOPC1 C0DIR IOPC0 PCDATDIR B3DIR IOPB3 B2DIR IOPB2 B1DIR IOPB1 B0DIR IOPB0 PBDATDIR A3DIR IOPA3 A2DIR IOPA2 A1DIR IOPA1 A0DIR IOPA0 PADATDIR MCRC.11 MCRC.3 E3DIR IOPE3 F3DIR IOPF3 MCRC.10 MCRC.2 E2DIR IOPE2 F2DIR IOPF2 MCRC.9 MCRC.1 E1DIR IOPE1 F1DIR IOPF1 MCRC.8 MCRC.0 E0DIR IOPE0 F0DIR IOPF0 PFDATDIR PEDATDIR MCRC MCRB.10 MCRB.2 MCRB.9 MCRB.1 MCRB.8 MCRB.0 MCRB MCRA.10 MCRA.2 MCRA.9 MCRA.1 MCRA.8 MCRA.0
MCRA.7
07091h 07092h 07093h 07094h
MCRB.7
MCRC.7 E7DIR
07095h
IOPE7 --
07096h 07097h 07098h 07099h 0709Ah 0709Bh 0709Ch 0709Dh 0709Eh 0709Fh
--
IOPA7
IOPB7
IOPC7
IOPD7
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PRODUCT PREVIEW
07090h
MCRA
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description (continued)
Table 15. LF2401A DSP Peripheral Register Description (Continued)
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS -- 070A0h CONV PRESCALE (CPS) EVB SOC EN SEQ1 070A1h EXT SOC EN SEQ1 -- 070A2h -- CONV 3 070A3h ADC S/W RESET CONTINUOUS RUN Reset SEQ1 Start CALIB Reset SEQ2 -- MAXCONV2 2 CONV 3 CONV 1 CONV 7 CONV 5 CONV 11 CONV 9 CONV 15 CONV 13 -- SEQ2 STATE 2 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 SOFT INT PRIORITY SOC SEQ1 SOC SEQ2 -- MAXCONV2 1 CONV 3 CONV 1 CONV 7 CONV 5 CONV 11 CONV 9 CONV 15 CONV 13 -- SEQ2 STATE 1 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 FREE ACQ PRESCALE3 CALIB EN INT ENA SEQ1 Mode1 INT ENA SEQ2 Mode1 -- MAXCONV1 3 CONV 2 CONV 0 CONV 6 CONV 4 CONV 10 CONV 8 CONV 14 CONV 12 SEQ CNTR3 SEQ1 STATE 3 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 ACQ PRESCALE2 BRIDGE EN INT ENA SEQ1 Mode0 INT ENA SEQ2 Mode0 -- MAXCONV1 2 CONV 2 CONV 0 CONV 6 CONV 4 CONV 10 CONV 8 CONV 14 CONV 12 SEQ CNTR2 SEQ1 STATE 2 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 ACQ PRESCALE1 HI / LO INT FLAG SEQ1 INT FLAG SEQ2 -- MAXCONV1 1 CONV 2 CONV 0 CONV 6 CONV 4 CONV 10 CONV 8 CONV 14 CONV 12 SEQ CNTR1 SEQ1 STATE 1 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 00 D3 0 ACQ PRESCALE0 ADCCTRL1 FSTEST EN EVA SOC EN SEQ1 EVB SOC EN SEQ2 -- MAXCONV1 0 CONV 2 CONV 0 CONV 6 CONV 4 CONV 10 CONV 8 CONV 14 CONV 12 SEQ CNTR0 SEQ1 STATE 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 RESULT7 RESULT6 RESULT5 RESULT4 RESULT3 RESULT2 RESULT1 RESULT0 AUTO_SEQ_SR CHSELSEQ4 CHSELSEQ3 CHSELSEQ2 CHSELSEQ1 MAXCONV ADCCTRL2
SEQ1/2 CASCADE
SEQ1 BUSY SEQ2 BUSY -- MAXCONV2 0 CONV 3 CONV 1 CONV 7 CONV 5 CONV 11 CONV 9 CONV 15 CONV 13 -- SEQ2 STATE 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0
PRODUCT PREVIEW
CONV 1 CONV 7
070A4h
CONV 5 CONV 11
070A5h
CONV 9 CONV 15
070A6h
CONV 13 --
070A7h
SEQ2 STATE 3 D9
070A8h
D1 D9
070A9h
D1 D9
070AAh
D1 D9
070ABh
D1 D9
070ACh
D1 D9
070ADh
D1 D9
070AEh
D1 D9
070AFh
D1
These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device.
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description (continued)
Table 15. LF2401A DSP Peripheral Register Description (Continued)
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS (CONTINUED) D9 070B0h D1 D9 070B1h D1 D9 070B2h D1 D9 070B3h D1 D9 070B4h D1 D9 070B5h D1 D9 070B6h D1 D9 070B7h D1 D9 070B8h 070B9h to 070FFh 07100h to 073FFh D1 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0 Illegal D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 RESULT12 RESULT11 RESULT10 RESULT9 RESULT8
D2 0 D2 0 D2 0 CALIBRATION RESULT15 RESULT14
Reserved GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS - EVA -- T2STAT TCOMPOE D14 D6 D14 D6 D14 D6 SOFT TENABLE D13 D5 D13 D5 D13 D5 -- TCLKS1 T1STAT -- D12 D4 D12 D4 D12 D4 TMODE1 TCLKS0 D11 D3 D11 D3 D11 D3 TMODE0 TCLD1 -- T2PIN D10 D2 D10 D2 D10 D2 TPS2 TCLD0 D9 D1 D9 D1 D9 D1 TPS1 TECMPR T2TOADC T1TOADC(1) T1PIN D8 D0 D8 D0 D8 D0 TPS0 -- T1CON T1PR T1CMPR T1CNT GPTCONA
07400h
T1TOADC(0) D15
07401h
D7 D15
07402h
D7 D15
07403h
D7 FREE
07404h
--
These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the correa licable eri heral sponding pins have not been bonded out of the device.
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PRODUCT PREVIEW
0
RESULT13
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description (continued)
Table 15. LF2401A DSP Peripheral Register Description (Continued)
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS - EVA (CONTINUED) D15 07405h D7 D15 07406h D7 D15 07407h D7 FREE 07408h 07409h to 07410h T2SWT1 D14 D6 D14 D6 D14 D6 SOFT TENABLE D13 D5 D13 D5 D13 D5 -- TCLKS1 D12 D4 D12 D4 D12 D4 TMODE1 TCLKS0 D11 D3 D11 D3 D11 D3 TMODE0 TCLD1 Illegal FULL AND SIMPLE COMPARE UNIT REGISTERS - EVA D10 D2 D10 D2 D10 D2 TPS2 TCLD0 D9 D1 D9 D1 D9 D1 TPS1 TECMPR D8 D0 D8 D0 D8 D0 TPS0 SELT1PR T2CON T2PR T2CMPR T2CNT
PRODUCT PREVIEW
CENABLE 07411h -- 07412h SVRDIR 07413h 07414h -- 07415h 07416h D15 07417h D7 D15 07418h D7 D15 07419h 0741Ah to 0741Fh D7 EDBT3 CMP4ACT1
CLD1 --
CLD0 --
SVENABLE --
ACTRLD1 -- Illegal
ACTRLD0 --
FCOMPOE --
PDPINTA STATUS --
COMCONA
D2 CMP4ACT0
D1 CMP3ACT1
D0 CMP3ACT0
CMP6ACT1 CMP2ACT1 Illegal
CMP6ACT0 CMP2ACT0
CMP5ACT1 CMP1ACT1
CMP5ACT0 CMP1ACT0 ACTRA
-- EDBT2
-- EDBT1
-- DBTPS2
DBT3 DBTPS1 Illegal
DBT2 DBTPS0
DBT1 --
DBT0 -- DBTCONA
D14 D6 D14 D6 D14 D6
D13 D5 D13 D5 D13 D5
D12 D4 D12 D4 D12 D4 Illegal
D11 D3 D11 D3 D11 D3
D10 D2 D10 D2 D10 D2
D9 D1 D9 D1 D9 D1
D8 D0 D8 D0 D8 D0 CMPR3 CMPR2 CMPR1
These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the correa licable eri heral sponding pins have not been bonded out of the device.
70
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TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description (continued)
Table 15. LF2401A DSP Peripheral Register Description (Continued)
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
CAPTURE UNIT REGISTERS - EVA CAPRES 07420h 07421h -- 07422h -- D15 07423h D7 D15 07424h D7 D15 07425h 07426h D15 07427h D7 D15 07428h D7 D15 07429h 0742Ah to 0742Bh D7 D14 D6 D14 D6 D14 D6 D13 D5 D13 D5 D13 D5 D12 D4 D12 D4 D12 D4 Illegal EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS -- 0742Ch T1PINT ENA -- 0742Dh -- -- 0742Eh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CMP3INT ENA -- T2OFINT ENA -- -- T1OFINT ENA CMP2INT ENA -- T2UFINT ENA -- CAP3INT ENA T1UFINT ENA CMP1INT ENA -- T2CINT ENA -- CAP2INT ENA T1CINT ENA PDPINTA ENA -- T2PINT ENA -- CAP1INT ENA EVAIMRC EVAIMRB EVAIMRA D7 -- D14 D6 D14 D6 D14 D6 -- D13 D5 D13 D5 D13 D5 CAP3FIFO -- D12 D4 D12 D4 D12 D4 Illegal D11 D3 D11 D3 D11 D3 D10 D2 D10 D2 D10 D2 D9 D1 D9 D1 D9 D1 D8 D0 D8 D0 D8 D0 CAP3FBOT CAP2FBOT CAP1FBOT -- D11 D3 D11 D3 D11 D3 CAP1EDGE CAPQEPN CAP3EN CAP2EDGE Illegal CAP2FIFO -- D10 D2 D10 D2 D10 D2 -- D9 D1 D9 D1 D9 D1 CAP1FIFO -- D8 D0 D8 D0 D8 D0 CAP3FIFO CAP2FIFO CAP1FIFO CAPFIFOA -- CAP3TSEL CAP3EDGE CAP12TSEL -- CAP3TOADC CAPCONA
These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the correa licable eri heral sponding pins have not been bonded out of the device.
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71
PRODUCT PREVIEW
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
peripheral register description (continued)
Table 15. LF2401A DSP Peripheral Register Description (Continued)
ADDR BIT 15 BIT 7 BIT 14 BIT 6 BIT 13 BIT 5 BIT 12 BIT 4 BIT 11 BIT 3 BIT 10 BIT 2 BIT 9 BIT 1 BIT 8 BIT 0 REG
EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS (CONTINUED) -- 0742Fh T1PINT FLAG -- 07430h -- -- 07431h 07432h to 074FFh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CMP3INT FLAG -- T2OFINT FLAG -- -- T1OFINT FLAG CMP2INT FLAG -- T2UFINT FLAG -- CAP3INT FLAG T1UFINT FLAG CMP1INT FLAG -- T2CINT FLAG -- CAP2INT FLAG T1CINT FLAG PDPINTA FLAG -- T2PINT FLAG -- CAP1INT FLAG EVAIFRC EVAIFRB EVAIFRA
Illegal
PRODUCT PREVIEW
07500h to 0753Fh
Reserved I/O MEMORY SPACE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FCMR
0FF0Fh
--
WAIT-STATE GENERATOR CONTROL REGISTER -- 0FFFFh ISWS.1 -- ISWS.0 -- DSWS.2 -- DSWS.1 -- DSWS.0 BVIS.1 PSWS.2 BVIS.0 PSWS.1 ISWS.2 PSWS.0 WSGR
These bits are not applicable in the LF2401A since either (i) the peripheral functionality is absent or (ii) the correa licable eri heral sponding pins have not been bonded out of the device.
72
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* HOUSTON, TEXAS 77251-1443
TMS320LF2401A DSP CONTROLLER
SPRS161 - MARCH 2001
MECHANICAL DATA
VF (S-PQFP-G32) PLASTIC QUAD FLATPACK
0,80 24 17
0,45 0,25
0,20 M
25
16
0,13 NOM 1 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0,10 0,75 0,45 0,25 0- 7 8
Gage Plane
4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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73
PRODUCT PREVIEW
32
9
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